Inter-chip communication bandwidth limitations threaten the continued growth in the amount of data that can be handled by conventional electronics. The demand for such bandwidth appears insatiable, doubling every three years (driven largely by the growth in multimedia communications). Although intra-chip integrated-circuit (IC) density has been doubling approximately every two years, a practical chip-size limit has led to many electronic systems having their functionality distributed across multiple integrated-circuit die. Unfortunately, the ability to communicate at high rates between chips has not been keeping pace with the bandwidth demand.
Aggregate inter-chip communications rates are limited, in part, by electrical and thermal considerations of the interconnect technology used to combine the different die on a common underlying substrate. The most dominant chip-to-chip interconnect technology is wire bonding, wherein lengths of small-diameter wires are bonded to input/output pads located on the periphery of the different IC chips. Unfortunately, the amount of periphery available for bond pads is limited and wire bonding to bond pads located in the interior of a chip is complex and expensive. In addition, wire bonds must be spaced somewhat sparsely to mitigate electrical cross-talk between them, as well as to provide room for the bonding equipment used to attach the wires to the chips. Further, wire bonds are normally quite long and characterized by high parasitic electrical inductance, which limits the frequency of the signals each wire bond can carry. Finally, significant power is needed to drive electrical signals over wire bonds, which leads to a need for relatively high power dissipation by the input/output pad driver circuits used. This power dissipation gives rise to heat that must be effectively removed for proper circuit operation.
Alternative packaging approaches have been developed to mitigate some of these problems. One such alternative technology is the ball-grid array-based (BGA-based) multi-chip module, which relies upon two-dimensional arrays of solder bumps formed on bond pads distributed throughout the area of an IC die. In some cases, the ball grid is formed on the same surfaces as the circuit elements of each semiconductor die and the chips are flipped over and bonded to an array of bond pads located on the common substrate. In other BGA approaches, electrically conductive “pipes” are formed through the thickness of the individual die substrates. These “through-wafer vias” enable the chips to be bonded, right-side-up, to the bond pads of their common substrate.
Solder bumps are characterized by lower inductance than conventional wire bonds due, in part, to the short distance of the electrical interconnect. In addition, solder bumps can be formed with higher density than wire bonds, and can be located within the interior of the IC chip. As a result, BGA-based packaging enables a significant improvement in aggregate I/O bandwidth over that of wire-bond based packaging.
While BGA-based packaging technology represents a significant advance over wire-bond-based multi-chip packaging, it is primarily limited to “2.5D” layouts (a single layer of attached die) and has significant shortcomings as well. First, the solder bumps serve a dual purpose in that they both electrically interconnect and physically join the individual die to the common substrate. As the semiconductor die heat up during operation, however, individual die undergo thermal expansion that changes the spacing of their bond pads. This places physical stress on the solder bumps, which lead to reliability issues and even catastrophic failure of the solder joints. This differential thermal expansion issue is particularly troubling for die have substrates of different materials, such as multi-chip modules containing silicon-based circuitry and compound-semiconductor-based optoelectronic chips.
Second, the degree of compression imparted on the solder bumps during bonding must be carefully controlled to effect suitable electrical connectivity without causing damage to the bonded die or the receiving substrate.
Third, the heat transfer capability of BGA-based packaging is limited by the total cross-sectional area of the solder bumps themselves, since the surfaces of the die and substrate between the solder joints are not normally in physical contact.
Finally, the mechanical integrity of the packaged system relies solely on the strength of the solder bumps themselves.
Flowing a thermally conductive material into the open space between a bump-bonded die and its underlying substrate is used to enhance the mechanical integrity of a package and facilitating conduction of heat from the bonded die to the common substrate.
While conventional underfill materials are seen as an improvement, their thermal conductivity has typically been relatively poor. As a result, efforts to increase the thermal conductivity of underfill materials is ongoing. For example, Ha, et al. reported liquid-dispensed underfill materials comprising adhesive-resins impregnated with high-thermal-conductivity constituents (e.g., graphene) in “Thermal conductivity of graphite filled liquid crystal polymer composites and theoretical predictions,” Compos. Sci. Tech., Vol. 88, pp. 113-119 (2013). Similarly, Brunschwiler, et al., reported on liquid-dispensed underfill materials suitable for forming interfacial layers between stacked die, where the underfill material includes thermally conductive filler particles that are physically connected by nanoparticle-based bridges in “Formulation of Percolating Thermal Underfills Using Hierarchical Self-Assembly of Microparticles and Nanoparticles by Centrifugal Forces and Capillary Bridging,” J. Microelectron. Electron. Packag., Vol. 9, pp. 149-159 (2012) and “Enhanced Electrical and Thermal Interconnects by the Self-Assembly of Nanoparticle Necks Utilizing Capillary Bridging,” J. Electron. Packag., Vol. 136, pg. 41012, (2014).
Unfortunately, while such approaches are conceptually attractive, they have yet to be demonstrated in practical packaging systems. Each of these prior-art approaches suffers from the lack of a technique for precise manipulation and controllable placement of high thermal conductivity materials, where the technique is easily scalable to large macro-scale areas.
As the drive toward ever-higher integration density continues, additional layers of active die are being placed in the vertical space above a common substrate, giving rise to three-dimensional (3D) packaging (a.k.a., vertical integration). Unfortunately, as the number of layers of active devices increases, the problems outlined above become more challenging. In particular, it becomes even harder to remove heat generated by active circuitry, which exacerbates the difficulty of accommodating the thermal expansion of individual chips. Low thermal conductance between vertically integrated device dies is considered to be a principal bottleneck for thermal management and currently available underfill materials are seen as inadequate.
A practical means of simultaneously providing good thermal conductivity, electrical insulation and mechanically compliance between semiconductor die of a vertically stacked electronics package remains unrealized in the current state of the art.